Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario
Los códigos de productos
DEMO9S12XHY256
Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
130
Freescale Semiconductor
2.3.67
Port R Data Direction Register (DDRR)
Address 0x0282
Access: User read/write
1
1
Read: Anytime.
Write: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
DDRR7
DDRR6
DDRR5
DDRR4
DDRR3
DDRR2
DDRR1
DDRR0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-64. Port R Data Direction Register (DDRR)
Table 2-54. DDRR Register Field Descriptions
Field
Description
7
DDRR
Port R data direction—
This register controls the data direction of pin 7.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled.
This register controls the data direction of pin 7.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0 Associated pin is configured as input.
6
DDRR
Port R data direction—
This register controls the data direction of pin 6.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled
Else If IIC is routing to PR and IIC is enabled, it will force as open-drain output.
This register controls the data direction of pin 6.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled
Else If IIC is routing to PR and IIC is enabled, it will force as open-drain output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0 Associated pin is configured as input.
5
DDRR
Port R data direction—
This register controls the data direction of pin 5.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled
Else If IIC is routing to PR and IIC is enabled, it will force as open-drain output.
This register controls the data direction of pin 5.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled
Else If IIC is routing to PR and IIC is enabled, it will force as open-drain output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0 Associated pin is configured as input.
4
DDRR
Port R data direction—
This register controls the data direction of pin 4.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled.
This register controls the data direction of pin 4.This register configures pin as either input or output.
If LCD segment driver output is enabled, it will force as input/output disabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0 Associated pin is configured as input.
3-2
DDRR
Port R data direction—
This register controls the data direction of pin 3-2.This register configures pin as either input or output.
If TIM1/ are routing to the PR and TIM1 output compare functions are enabled, it will force as output.
This register controls the data direction of pin 3-2.This register configures pin as either input or output.
If TIM1/ are routing to the PR and TIM1 output compare functions are enabled, it will force as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0 Associated pin is configured as input.