Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario
Los códigos de productos
DEMO9S12XHY256
Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
139
2.3.83
Port U Data Direction Register (DDRU)
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTU or PTIU registers, when changing the
DDRU register.
until the correct value is read on PTU or PTIU registers, when changing the
DDRU register.
2.3.84
PIM Reserved Registers
Address 0x0292
Access: User read/write
1
1
Read: Anytime.
Write: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
DDRU7
DDRU6
DDRU5
DDRU4
DDRU3
DDRU2
DDRU1
DDRU0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-80. Port U Data Direction Register (DDRU)
Table 2-68. DDRU Register Field Descriptions
Field
Description
7,5,3,1
DDRU
Port U data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output.
If enabled the Motor driver PWM output it will force the I/O state to be output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0 Associated pin is configured as input.
6,4,2,0
DDRU
Port U data direction—
If enabled the Motor driver PWM output it will force the I/O state to be output.
Else if corresponding TIM0 output compare channel is enabled, it will be force as output
If enabled the Motor driver PWM output it will force the I/O state to be output.
Else if corresponding TIM0 output compare channel is enabled, it will be force as output
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0 Associated pin is configured as input.
Address 0x0293
Access: User read
1
1
Read: Always reads 0x00
Write: Unimplemented
Write: Unimplemented
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-81. PIM Reserved Registers