Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario

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Freescale Semiconductor

The main features of this block are:

•

Paging capability to support a global 8MB memory address space

•

Bus arbitration between the masters CPU, BDM

•

Simultaneous accesses to different resources

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 (internal, and peripherals) (see

 )

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Resolution of target bus access collision

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MCU operation mode control

•

MCU security control

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Separate memory map schemes for each master CPU, BDM

•

ROM control bits to enable the on-chip FLASH or ROM selection

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Generation of system reset when CPU accesses an unimplemented address (i.e., an address which
does not belong to any of the on-chip modules) in single-chip modes

Logic level “1”

Voltage that corresponds to Boolean true state

Logic level “0”

Voltage that corresponds to Boolean false state

0x

Represents hexadecimal number

x

Represents logic level ’don’t care’

Byte

8-bit data

word

16-bit data

local address

based on the 64KB Memory Space (16-bit address)

global address

based on the 8MB Memory Space (23-bit address)

Aligned address

Address on even boundary

Mis-aligned address

Address on odd boundary

Bus Clock

System Clock. Refer to CRG Block Guide.

single-chip modes

Normal Single-Chip Mode
Special Single-Chip Mode

normal modes

Normal Single-Chip Mode

special modes

Special Single-Chip Mode

NS

Normal Single-Chip Mode

SS

Special Single-Chip Mode

Unimplemented areas

Areas which are accessible by the pages (RPAGE,PPAGE,EPAGE) and not implemented

PRR

Port Replacement Registers

PRU

Port Replacement Unit located on the emulator side

MCU

MicroController Unit

NVM

Non-volatile Memory; Flash, Data FLASH or ROM

IFR

Information Row sector located on the top of NVM. For Test purposes.

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Resources are also called targets.