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S12X Debug (S12XDBGV3) Module
MC9S12XHY-Family Reference Manual Rev. 1.04
Freescale Semiconductor
243
6.3.2.8.3
Debug Comparator Address Mid Register (DBGXAM)
Read: Anytime. See
 for visible register encoding.
Write: If DBG not armed. See
 for visible register encoding.
6.3.2.8.4
Debug Comparator Address Low Register (DBGXAL)
Read: Anytime. See
 for visible register encoding.
Write: If DBG not armed. See
 for visible register encoding.
Address: 0x002A
7
6
5
4
3
2
1
0
R
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
W
Reset
0
0
0
0
0
0
0
0
Figure 6-16. Debug Comparator Address Mid Register (DBGXAM)
Table 6-30. DBGXAM Field Descriptions
Field
Description
7–0
Bit[15:8]
Comparator Address Mid Compare Bits— The Comparator address mid compare bits control whether the
selected comparator will compare the address bus bits [15:8] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one
Address: 0x002B
7
6
5
4
3
2
1
0
R
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 6-17. Debug Comparator Address Low Register (DBGXAL)
Table 6-31. DBGXAL Field Descriptions
Field
Description
7–0
Bits[7:0]
Comparator Address Low Compare Bits — The Comparator address low compare bits control whether the
selected comparator will compare the address bus bits [7:0] to a logic one or logic zero.
0 Compare corresponding address bit to a logic zero
1 Compare corresponding address bit to a logic one