Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario

Freescale Semiconductor

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If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block
generates a clock monitor fail event. The S12XECRG then asserts self clock mode or generates a system
reset depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is
detected no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by
the CME control bit.

The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker
provides a more accurate check in addition to the clock monitor.

A clock quality check is triggered by any of the following events:

•

Power on reset (POR)

•

Low voltage reset (LVR)

•

Wake-up from Full Stop Mode (exit full stop)

•

Clock Monitor fail indication (CM fail)

A time window of 50000 PLLCLK cycles

6

 is called check window.

A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that
osc ok immediately terminates the current check window. See

 as an example.

6. IPLL is running at self clock mode frequency f

SCM

.

1

2

49999

50000

PLLCLK

CHECK WINDOW

1

2

3

4

5

4095

4096

3

OSCCLK

OSC OK