Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario

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Freescale Semiconductor

Due to the nature of VREG_3V3 being a voltage regulator providing the chip internal power supply
voltages, most signals are power supply signals connected to pads.

 shows all signals of VREG_3V3 associated with pins.

Check device level specification for connectivity of the signals.

Signal VDDR is the power input of VREG_3V3. All currents sourced into the regulator loads flow through
this pin. A chip external decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDR and VSSR
(if VSSR is not available VSS) can smooth ripple on VDDR.

For entering Shutdown Mode, pin VDDR should also be tied to ground on devices without VREGEN pin.

Signals VDDA/VSSA

,

which are supposed to be relatively quiet, are used to supply the analog parts of the

regulator. Internal precision reference circuits are supplied from these signals. A chip external decoupling
capacitor (100 nF...220 nF, X7R ceramic) between VDDA and VSSA can further improve the quality of
this supply.

Signals VDD/VSS are the primary outputs of VREG_3V3 that provide the power supply for the core logic.
These signals are connected to device pins to allow external decoupling capacitors (220 nF, X7R ceramic).

VDDR

Power input (positive supply)

—

—

VDDA

Quiet input (positive supply)

—

—

VSSA

Quiet input (ground)

—

—

VDDX

Power input (positive supply)

—

—

VDD

Primary output (positive supply)

—

 —

VSS

Primary output (ground)

—

—

VDDF

Secondary output (positive supply)

—

—

VDDPLL

Tertiary output (positive supply)

—

—

VSSPLL

Tertiary output (ground)

—

 —

VREGEN (optional)

Optional Regulator Enable

—

—

VREG_API

(optional)

VREG Autonomous Periodical
Interrupt output

—

—