Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario

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Freescale Semiconductor

It is possible to generate with the API a waveform at an external pin by enabling the API by setting APIFE
and enabling the external access with setting APIEA. By setting APIES the waveform can be selected. If
APIES is set, then at the external pin a clock is visible with 2 times the selected API Period (

).

If APIES is not set, then at the external pin will be a high pulse at the end of every selected period with the
size of half of the min period (

). See device level specification for connectivity.

This section describes how VREG_3V3 controls the reset of the MCU.The reset values of registers and
signals are provided in

. Possible reset sources are

listed in

During chip power-up the digital core may not work if its supply voltage V

DD

 is below the POR

deassertion level (V

PORD

). Therefore, signal POR, which forces the other blocks of the device into reset,

is kept high until V

DD

 exceeds V

PORD

. The MCU will run the start-up sequence after POR deassertion.

The power-on reset is active in all operation modes of VREG_3V3.

For details on low-voltage reset, see

.

This section describes all interrupts originated by VREG_3V3.

The interrupt vectors requested by VREG_3V3 are listed in

. Vector addresses and interrupt

priorities are defined at MCU level.

Power-on reset

Always active

Low-voltage reset

Available only in Full Performance Mode

Low-voltage interrupt (LVI)

LVIE = 1; available only in Full Performance

Mode

High Temperature Interrupt (HTI)

HTIE=1;

available only in Full Performance Mode

Autonomous periodical interrupt (API)

APIE = 1