Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario
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DEMO9S12XHY256
Analog-to-Digital Converter (ADC12B12CV1) Block Description
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
327
10.3.2.6
ATD Control Register 5 (ATDCTL5)
Writes to this register will abort current conversion sequence and start a new conversion sequence. If
external trigger is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a
conversion sequence which will then occur on each trigger event. Start of conversion means the beginning
of the sampling phase.
external trigger is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting of a
conversion sequence which will then occur on each trigger event. Start of conversion means the beginning
of the sampling phase.
Read: Anytime
Write: Anytime
Module Base + 0x0005
7
6
5
4
3
2
1
0
R
0
SC
SCAN
MULT
CD
CC
CB
CA
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-8. ATD Control Register 5 (ATDCTL5)
Table 10-14. ATDCTL5 Field Descriptions
Field
Description
6
SC
Special Channel Conversion Bit — If this bit is set, then special channel conversion can be selected using CD,
CC, CB and CA of ATDCTL5.
CC, CB and CA of ATDCTL5.
0 Special channel conversions disabled
1 Special channel conversions enabled
1 Special channel conversions enabled
5
SCAN
Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed
continuously or only once. If external trigger is enabled (ETRIGE=1) setting this bit has no effect, that means
external trigger always starts a single conversion sequence.
0 Single conversion sequence
1 Continuous conversion sequences (scan mode)
continuously or only once. If external trigger is enabled (ETRIGE=1) setting this bit has no effect, that means
external trigger always starts a single conversion sequence.
0 Single conversion sequence
1 Continuous conversion sequences (scan mode)
4
MULT
Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified
analog input channel for an entire conversion sequence. The analog channel is selected by channel selection
code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples
across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C,
S1C). The first analog channel examined is determined by channel selection code (CD, CC, CB, CA control bits);
subsequent channels sampled in the sequence are determined by incrementing the channel selection code or
wrapping around to AN0 (channel 0).
0 Sample only one channel
1 Sample across several channels
analog input channel for an entire conversion sequence. The analog channel is selected by channel selection
code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples
across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C,
S1C). The first analog channel examined is determined by channel selection code (CD, CC, CB, CA control bits);
subsequent channels sampled in the sequence are determined by incrementing the channel selection code or
wrapping around to AN0 (channel 0).
0 Sample only one channel
1 Sample across several channels
3–0
CD, CC,
CB, CA
Analog Input Channel Select Code — These bits select the analog input channel(s) whose signals are
sampled and converted to digital codes.
sampled and converted to digital codes.
lists the coding used to select the various analog input
channels.
In the case of single channel conversions (MULT=0), this selection code specifies the channel to be examined.
In the case of multiple channel conversions (MULT=1), this selection code specifies the first channel to be
examined in the conversion sequence. Subsequent channels are determined by incrementing the channel
selection code or wrapping around to AN0 (after converting the channel defined by the Wrap Around Channel
Select Bits WRAP3-0 in ATDCTL0). In case of starting with a channel number higher than the one defined by
WRAP3-0 the first wrap around will be AN7 to AN0.
examined in the conversion sequence. Subsequent channels are determined by incrementing the channel
selection code or wrapping around to AN0 (after converting the channel defined by the Wrap Around Channel
Select Bits WRAP3-0 in ATDCTL0). In case of starting with a channel number higher than the one defined by
WRAP3-0 the first wrap around will be AN7 to AN0.