Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario
Los códigos de productos
DEMO9S12XHY256
Freescale’s Scalable Controller Area Network (S12MSCANV3)
MC9S12XHY-Family Reference Manual Rev. 1.04
Freescale Semiconductor
355
NOTE
The CANTFLG register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
mode is active (INITRQ = 1 and INITAK = 1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
11.3.2.8
MSCAN Transmitter Interrupt Enable Register (CANTIER)
This register contains the interrupt enable bits for the transmit buffer empty interrupt flags.
Module Base + 0x0006
Access: User read/write
(1)
1. Read: Anytime
Write: Anytime when not in initialization mode; write of 1 clears flag, write of 0 is ignored
7
6
5
4
3
2
1
0
R
0
0
0
0
0
TXE2
TXE1
TXE0
W
Reset:
0
0
0
0
0
1
1
1
= Unimplemented
Figure 11-10. MSCAN Transmitter Flag Register (CANTFLG)
Table 11-13. CANTFLG Register Field Descriptions
Field
Description
2-0
TXE[2:0]
Transmitter Buffer Empty — This flag indicates that the associated transmit message buffer is empty, and thus
not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and
is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by
the MSCAN when the transmission request is successfully aborted due to a pending abort request (see
not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and
is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by
the MSCAN when the transmission request is successfully aborted due to a pending abort request (see
”). If not masked, a
transmit interrupt is pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx (see
Clearing a TXEx flag also clears the corresponding ABTAKx (see
”). When a TXEx flag is set, the corresponding ABTRQx bit
is cleared (see
When listen-mode is active (see
”) the TXEx flags
cannot be cleared and no transmission is started.
Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared
(TXEx = 0) and the buffer is scheduled for transmission.
0 The associated message buffer is full (loaded with a message due for transmission)
1 The associated message buffer is empty (not scheduled)
Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared
(TXEx = 0) and the buffer is scheduled for transmission.
0 The associated message buffer is full (loaded with a message due for transmission)
1 The associated message buffer is empty (not scheduled)
Module Base + 0x0007
Access: User read/write
(1)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
TXEIE2
TXEIE1
TXEIE0
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)