Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario
Los códigos de productos
DEMO9S12XHY256
Inter-Integrated Circuit (IICV3) Block Description
MC9S12XHY-Family Reference Manual, Rev. 1.04
404
Freescale Semiconductor
Note:Since the bus frequency is speeding up,the SCL Divider could be expanded by it.Therefore,in the
table,when IBC[7:0] is from $00 to $0F,the SCL Divider is revised by the format value1/value2.Value1 is
the divider under the low frequency.Value2 is the divider under the high frequency.How to select the
divider depends on the bus frequency.When IBC[7:0] is from $10 to $BF,the divider is not changed.
table,when IBC[7:0] is from $00 to $0F,the SCL Divider is revised by the format value1/value2.Value1 is
the divider under the low frequency.Value2 is the divider under the high frequency.How to select the
divider depends on the bus frequency.When IBC[7:0] is from $10 to $BF,the divider is not changed.
12.3.1.3
IIC Control Register (IBCR)
Read and write anytime
B2
3584
516
1784
1796
B3
4096
516
2040
2052
B4
4608
772
2296
2308
B5
5120
772
2552
2564
B6
6144
1028
3064
3076
B7
7680
1028
3832
3844
B8
5120
516
2552
2564
B9
6144
516
3064
3076
BA
7168
1028
3576
3588
BB
8192
1028
4088
4100
BC
9216
1540
4600
4612
BD
10240
1540
5112
5124
BE
12288
2052
6136
6148
BF
15360
2052
7672
7684
Module Base + 0x0002
7
6
5
4
3
2
1
0
R
IBEN
IBIE
MS/SL
Tx/Rx
TXAK
0
0
IBSWAI
W
RSTA
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-6. IIC Bus Control Register (IBCR)
Table 12-7. IIC Divider and Hold Values (Sheet 6 of 6)
IBC[7:0]
(hex)
SCL Divider
(clocks)
SDA Hold
(clocks)
SCL Hold
(start)
SCL Hold
(stop)