Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario

Freescale Semiconductor

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clock and the SCL period it may be necessary to wait until the IIC is busy after writing the calling address
to the IBDR before proceeding with the following instructions. This is illustrated in the following example.

An example of a program which generates the START signal and transmits the first byte of data (slave
address) is shown below:

Transmission or reception of a byte will set the data transferring bit (TCF) to 1, which indicates one byte
communication is finished. The IIC bus interrupt bit (IBIF) is set also; an interrupt will be generated if the
interrupt function is enabled during initialization by setting the IBIE bit. Software must clear the IBIF bit
in the interrupt routine first. The TCF bit will be cleared by reading from the IIC bus data I/O register
(IBDR) in receive mode or writing to IBDR in transmit mode.

Software may service the IIC I/O in the main program by monitoring the IBIF bit if the interrupt function
is disabled. Note that polling should monitor the IBIF bit rather than the TCF bit because their operation
is different when arbitration is lost.

Note that when an interrupt occurs at the end of the address cycle the master will always be in transmit
mode, i.e. the address is transmitted. If master receive mode is required, indicated by R/W bit in IBDR,
then the Tx/Rx bit should be toggled at this stage.

During slave mode address cycles (IAAS=1), the SRW bit in the status register is read to determine the
direction of the subsequent transfer and the Tx/Rx bit is programmed accordingly.For slave mode data
cycles (IAAS=0) the SRW bit is not valid, the Tx/Rx bit in the control register should be read to determine
the direction of the current transfer.

The following is an example of a software response by a 'master transmitter' in the interrupt routine.

A data transfer ends with a STOP signal generated by the 'master' device. A master transmitter can simply
generate a STOP signal after all the data has been transmitted. The following is an example showing how
a stop condition is generated by a master transmitter.

CHFLAG

BRSET

IBSR,#$20,*

;WAIT FOR IBB FLAG TO CLEAR

TXSTART

BSET

IBCR,#$30

;SET TRANSMIT AND MASTER MODE;i.e. GENERATE START CONDITION

MOVB

CALLING,IBDR

;TRANSMIT THE CALLING ADDRESS, D0=R/W

IBFREE

BRCLR

IBSR,#$20,*

;WAIT FOR IBB FLAG TO SET

ISR

BCLR

IBSR,#$02

;CLEAR THE IBIF FLAG

BRCLR

IBCR,#$20,SLAVE

;BRANCH IF IN SLAVE MODE

BRCLR

IBCR,#$10,RECEIVE

;BRANCH IF IN RECEIVE MODE

BRSET

IBSR,#$01,END

;IF NO ACK, END OF TRANSMISSION

TRANSMIT

MOVB

DATABUF,IBDR

;TRANSMIT NEXT BYTE OF DATA