Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario
Los códigos de productos
DEMO9S12XHY256
Pulse-Width Modulator (S12PWM8B8CV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
431
13.3.2.5
PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be
center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See
outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be
center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See
and
for a more
detailed description of the PWM output modes.
Read: Anytime
Write: Anytime
NOTE
Write these bits only when the corresponding channel is disabled.
13.3.2.6
PWM Control Register (PWMCTL)
The PWMCTL register provides for various control of the PWM module.
Read: Anytime
Write: Anytime
There are three control bits for concatenation, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. When channels 6 and 7are concatenated, channel 6 registers become the
high order bytes of the double byte channel. When channels 4 and 5 are concatenated, channel 4 registers
become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel
channels into one 16-bit channel. When channels 6 and 7are concatenated, channel 6 registers become the
high order bytes of the double byte channel. When channels 4 and 5 are concatenated, channel 4 registers
become the high order bytes of the double byte channel. When channels 2 and 3 are concatenated, channel
Module Base + 0x0004
7
6
5
4
3
2
1
0
R
CAE7
CAE6
CAE5
CAE4
CAE3
CAE2
CAE1
CAE0
W
Reset
0
0
0
0
0
0
0
0
Figure 13-7. PWM Center Align Enable Register (PWMCAE)
Table 13-8. PWMCAE Field Descriptions
Field
Description
7–0
CAE[7:0]
Center Aligned Output Modes on Channels 7–0
0 Channels 7–0 operate in left aligned output mode.
1 Channels 7–0 operate in center aligned output mode.
0 Channels 7–0 operate in left aligned output mode.
1 Channels 7–0 operate in center aligned output mode.
Module Base + 0x0005
7
6
5
4
3
2
1
0
R
CON67
CON45
CON23
CON01
PSWAI
PFRZ
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-8. PWM Control Register (PWMCTL)