Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario
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DEMO9S12XHY256
Serial Communication Interface (S12SCIV5)
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
463
14.3.2.5
SCI Alternative Control Register 2 (SCIACR2)
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
Module Base + 0x0002
7
6
5
4
3
2
1
0
R
0
0
0
0
0
BERRM1
BERRM0
BKDFE
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-8. SCI Alternative Control Register 2 (SCIACR2)
Table 14-8. SCIACR2 Field Descriptions
Field
Description
2:1
BERRM[1:0]
Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See
.
0
BKDFE
Break Detect Feature Enable — BKDFE enables the break detect circuitry.
0 Break detect circuit disabled
1 Break detect circuit enabled
0 Break detect circuit disabled
1 Break detect circuit enabled
Table 14-9. Bit Error Mode Coding
BERRM1
BERRM0
Function
0
0
Bit error detect circuit is disabled
0
1
Receive input sampling occurs during the 9th time tick of a transmitted bit
(refer to
(refer to
1
0
Receive input sampling occurs during the 13th time tick of a transmitted bit
(refer to
(refer to
1
1
Reserved