Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario
Los códigos de productos
DEMO9S12XHY256
Serial Peripheral Interface (S12SPIV5)
MC9S12XHY-Family Reference Manual, Rev. 1.04
496
Freescale Semiconductor
15.3.2.2
SPI Control Register 2 (SPICR2)
Read: Anytime
Write: Anytime; writes to the reserved bits have no effect
1
SSOE
Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by
asserting the SSOE as shown in
asserting the SSOE as shown in
. In master mode, a change of this bit will abort a transmission in
progress and force the SPI system into idle state.
0
LSBFE
LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and
writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit
will abort a transmission in progress and force the SPI system into idle state.
0 Data is transferred most significant bit first.
1 Data is transferred least significant bit first.
writes of the data register always have the MSB in the highest bit position. In master mode, a change of this bit
will abort a transmission in progress and force the SPI system into idle state.
0 Data is transferred most significant bit first.
1 Data is transferred least significant bit first.
Table 15-2. SS Input / Output Selection
MODFEN
SSOE
Master Mode
Slave Mode
0
0
SS not used by SPI
SS input
0
1
SS not used by SPI
SS input
1
0
SS input with MODF feature
SS input
1
1
SS is slave select output
SS input
Module Base +0x0001
7
6
5
4
3
2
1
0
R
0
XFRW
0
MODFEN
BIDIROE
0
SPISWAI
SPC0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-4. SPI Control Register 2 (SPICR2)
Table 15-1. SPICR1 Field Descriptions (continued)
Field
Description