Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario
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DEMO9S12XHY256
Timer Module (TIM16B8CV2) Block Description
MC9S12XHY-Family Reference Manual, Rev. 1.04
526
Freescale Semiconductor
16.3.2.4
Output Compare 7 Data Register (OC7D)
Read: Anytime
Write: Anytime
16.3.2.5
Timer Count Register (TCNT)
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give a different result than accessing them as a word.
byte and low byte will give a different result than accessing them as a word.
Read: Anytime
Module Base + 0x0003
7
6
5
4
3
2
1
0
R
OC7D7
OC7D6
OC7D5
OC7D4
OC7D3
OC7D2
OC7D1
OC7D0
W
Reset
0
0
0
0
0
0
0
0
Figure 16-9. Output Compare 7 Data Register (OC7D)
Table 16-5. OC7D Field Descriptions
Field
Description
7:0
OC7D[7:0]
Output Compare 7 Data — A channel 7 event, which can be a counter overflow when TTOV[7] is set or a
successful output compare on channel 7, can cause bits in the output compare 7 data register to transfer to the
timer port data register depending on the output compare 7 mask register.
successful output compare on channel 7, can cause bits in the output compare 7 data register to transfer to the
timer port data register depending on the output compare 7 mask register.
Module Base + 0x0004
15
14
13
12
11
10
9
9
R
TCNT15
TCNT14
TCNT13
TCNT12
TCNT11
TCNT10
TCNT9
TCNT8
W
Reset
0
0
0
0
0
0
0
0
Figure 16-10. Timer Count Register High (TCNTH)
Module Base + 0x0005
7
6
5
4
3
2
1
0
R
TCNT7
TCNT6
TCNT5
TCNT4
TCNT3
TCNT2
TCNT1
TCNT0
W
Reset
0
0
0
0
0
0
0
0
Figure 16-11. Timer Count Register Low (TCNTL)