Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario
Los códigos de productos
DEMO9S12XHY256
Timer Module (TIM16B8CV2) Block Description
MC9S12XHY-Family Reference Manual Rev. 1.04
Freescale Semiconductor
531
Read: Anytime
Write: Anytime.
16.3.2.10 Timer Interrupt Enable Register (TIE)
Read: Anytime
Write: Anytime.
Table 16-11. TCTL3/TCTL4 Field Descriptions
Field
Description
7:0
EDGnB
EDGnA
EDGnA
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
circuits.
Table 16-12. Edge Detector Circuit Configuration
EDGnB
EDGnA
Configuration
0
0
Capture disabled
0
1
Capture on rising edges only
1
0
Capture on falling edges only
1
1
Capture on any edge (rising or falling)
Module Base + 0x000C
7
6
5
4
3
2
1
0
R
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
W
Reset
0
0
0
0
0
0
0
0
Figure 16-18. Timer Interrupt Enable Register (TIE)
Table 16-13. TIE Field Descriptions
Field
Description
7:0
C7I:C0I
Input Capture/Output Compare “x” Interrupt Enable — The bits in TIE correspond bit-for-bit with the bits in
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.
the TFLG1 status register. If cleared, the corresponding flag is disabled from causing a hardware interrupt. If set,
the corresponding flag is enabled to cause a interrupt.