Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario

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DEMO9S12XHY256

Device Overview MC9S12XHY-Family

MC9S12XHY-Family Reference Manual, Rev. 1.04

Freescale Semiconductor

1.12

COP Configuration

The COP time-out rate bits CR[2:0] and the WCOP bit in the COPCTL registerare loaded from the Flash
register FOPT. See

Table 1-12

and

Table 1-13

for coding. The FOPT register is loaded from the Flash

configuration field byte at global address 0x7_FF0E during the reset sequence.

If the MCU is secured the COP time-out rate is always set to the longest period (CR[2:0] = 111) after any
reset into Special Single Chip mode.{mcu_9s12xhy256_cop_resetval.s}

1.13

ATD External Trigger Input Connection

The ATD module includes external trigger inputs ETRIG[3:0]. The external trigger allows the user to
synchronize ATD conversion to external trigger events.

Table 1-14

shows the connection of the external

trigger inputs.

Table 1-12. Initial COP Rate Configuration

NV[2:0] in

FOPT Register

CR[2:0] in

COPCTL Register

000

111

001

110

010

101

011

100

011

101

010

110

001

111

000

Table 1-13. Initial WCOP Configuration

NV[3] in

FOPT Register

WCOP in

COPCTL Register

Table 1-14. ATD External Trigger Sources

External Trigger

Input

Connectivity

ETRIG0

PP1(PWM channel 1)

(1)

1. When LCD segment output driver is enabled on PP1/PP3, the ATD

external trigger function will be unavailable

ETRIG1

PP3(PWM channel 3)

ETRIG2

TIM0 Channel output 2

(2)

2. Independ on the TIM0OCPD3/2 bit setting

ETRIG3

TIM0 Channel output 3