Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario
Los códigos de productos
DEMO9S12XHY256
128 KByte Flash Module (S12XFTMR128K1V1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
642
Freescale Semiconductor
19.3.2.13 Flash Reserved1 Register (FRSV1)
This Flash register is reserved for factory testing.
All bits in the FRSV1 register read 0 and are not writable.
19.3.2.14 Flash ECC Error Results Register (FECCR)
The FECCR registers contain the result of a detected ECC fault for both single bit and double bit faults.
The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits
in the FECCRIX register (see
The FECCR register provides access to several ECC related fields as defined by the ECCRIX index bits
in the FECCRIX register (see
fault information will be recorded until the specific ECC fault flag has been cleared. In the event of
simultaneous ECC faults the priority for fault recording is double bit fault over single bit fault.
simultaneous ECC faults the priority for fault recording is double bit fault over single bit fault.
All FECCR bits are readable but not writable.
Offset Module Base + 0x000D
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-19. Flash Reserved1 Register (FRSV1)
Offset Module Base + 0x000E
7
6
5
4
3
2
1
0
R
ECCR[15:8]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-20. Flash ECC Error Results High Register (FECCRHI)
Offset Module Base + 0x000F
7
6
5
4
3
2
1
0
R
ECCR[7:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 19-21. Flash ECC Error Results Low Register (FECCRLO)