Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario

Freescale Semiconductor

727

 shows the configuration of the peripherals for typical run current.

Run current is measured on VDDR and VDDA pin. It does not include the current to drive external
loads.Currents are measured in single chip mode, S12XCPU with V

DD35

=5.5V, internal voltage regulator

enabled and a 40 MHz bus frequency from a 4 MHz input. Characterized parameters are derived using a
4 MHz loop controlled Pierce oscillator. Production test parameters are tested with a 4MHz square wave
oscillator.

S12XCPU

420 cycle loop: 384 DBNE cycles plus subroutine entry to stimulate stacking (RAM access)

COP & RTI

enabled. COP running at the rate 224, RTI control register(RTICTL) set to $7F

PLL

enabled and configured to supply the part with the maximum specified bus frequency (80 MHz).

DBG

the module is enabled and the comparators are configured to trigger in outside range.The range
covers all the code executed by the core,the tracing is disabled..

CAN0,CAN1

Configured to loop-back mode using a bit rate of 500kbit/s

SPI

Configured to master mode, continuously transmit data (0x55 or 0xAA) at 1 Mbit/s

SCI0,SCI1

Configured into loop mode, with the break detection and collision detection features enabled,
continuously transmit data (0x55) at speed of 19200 baud

PWM

Configured to toggle its pins at the rate of 1 kHz

IIC

operate in master mode and continuously transimit data(0x55 or 0xAA) at 100Kbits/s

LCD

configured to 244Hz frame frequency, 1/4 Duty, 1/3 Bias with all FP/BP enabled and all
segment on

MC

configured to full H-bridge mode MCPER=0x3FF, 1/2fbus motor controller timer counter
clock, MCDC=0x20

SSD

disabled

TIM0,TIM1

The peripheral shall be configured in output compare mode. Pulse accumulator and modulus
counter enabled.

ATD

The peripheral is configured to operate at its maximum specified
frequency and to continuously convert voltages on all input channels in sequence.

Overhead

VREG supplying 1.8V from a 5V input voltage, PLL on