Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario

Freescale Semiconductor

731

This section describes the characteristics of the analog-to-digital converter.

The

 show conditions under which the ATD operates.

The following constraints exist to obtain full-scale, full range results:

V

SSA

≤ V

RL

 ≤ V

IN

 ≤ V

RH

 ≤ V

DDA

.

This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that
it ties to. If the input level goes outside of this range it will effectively be clipped.

Source resistance, source capacitance and current injection have an influence on the accuracy of the ATD.
A further factor is that PortAD pins that are configured as output drivers switching.

PortAD output drivers switching can adversely affect the ATD accuracy whilst converting the analog
voltage on other PortAD pins because the output drivers are supplied from the VDDA/VSSA ATD supply
pins. Although internal design measures are implemented to minimize the affect of output driver noise, it

Conditions are shown in

 unless otherwise noted, supply voltage 3.13 V < V

DDA

 < 5.5 V

1

D Reference potential

Low
High

V

RL

V

RH

V

SSA

V

DDA

/2

—
—

V

DDA

/2

V

DDA

V
V

2

D Voltage difference V

DDX

 to V

DDA

∆

VDDX

–0.1

0

0.1

V

3

D Voltage difference V

SSX

 to V

SSA

∆

VSSX

–0.1

0

0.1

V

4

C Differential reference voltage

1

1

Full accuracy is not guaranteed when differential voltage is less than 4.50 V

V

RH

-V

RL

3.13

5.0

5.5

V

5

C ATD Clock Frequency (derived from bus clock via the

prescaler bus)

f

ATDCLk

0.25

—

8.3

MHz

6

P ATD Clock Frequency in Stop mode (internal generated

temperature and voltage dependent clock, ICLK)

0.6

1

1.7

MHz

7

D ADC conversion in stop, recovery time

2

2

When converting in Stop Mode (ICLKSTP=1) an ATD Stop Recovery time tATDSTPRCV is required to switch back to bus clock
based ATDCLK when leaving Stop Mode. Do not access ATD registers during this time.

t

ATDSTPRCV

—

—

1.5

µ

s

8

D

ATD Conversion Period

3

10 bit resolution:
8 bit resolution:

3

The minimum time assumes a sample time of 4 ATD clock cycles. The maximum time assumes a sample time of 24 ATD clock
cycles and the discharge feature (SMP_DIS) enabled, which adds 2 ATD clock cycles.

N

CONV10

N

CONV8

19
17

—
—

41
39

ATD

clock

cycles