Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario
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DEMO9S12XHY256
Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
97
2.3.20
PIM Reserved Register
2.3.21
Port T Routing Register (PTTRR)
This register configures the re-routing of TIM0/1 channels on alternative pins on Port R/T.
Address 0x0246
Access: User read
1
1
Read: Always reads 0x00
Write: Unimplemented
Write: Unimplemented
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-18. PIM Reserved Register
Address 0x0247
Access: User read
1
1
Read: Anytime
Write: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
PTTRR7
PTTRR6
PTTRR5
PTTRR4
PTTRR3
PTTRR2
PTTRR1
PTTRR0
W
Routing
Option
IOC0_7
IOC0_5
IOC0_4
IOC0_6
IOC1_7
IOC1_6
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-19. Port T Routing Register (PTTRR)
Table 2-16. Port T Routing Register Field Descriptions
Field
Description
[7:6]
PTTRR
Port T data direction—
This register controls the routing of IOC0_7.
This register controls the routing of IOC0_7.
00 IOC0_7 routed to PT7
01 IOC0_7 routed to PR1
10 IOC0_7 routed to PV6
11 IOC0_7 routed to PT7(reserved)
01 IOC0_7 routed to PR1
10 IOC0_7 routed to PV6
11 IOC0_7 routed to PT7(reserved)
5
PTTRR
Port T data direction—
This register controls the routing of IOC0_5.
This register controls the routing of IOC0_5.
0 IOC0_5 routed to PT5
1 IOC0_5 routed to PV2
1 IOC0_5 routed to PV2