Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT Hoja De Datos

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TWR-S12GN32-KIT

Device Overview MC9S12G-Family

MC9S12G Family Reference Manual,

Rev.1.23

150

Freescale Semiconductor

Table 1-34. Reset Sources and Vector Locations

1.12.2

Interrupt Vectors

Table 1-35

lists all interrupt sources and vectors in the default order of priority. The interrupt module (see

Chapter 6, “Interrupt Module (S12SINTV1)

”

) provides an interrupt vector base register (IVBR) to relocate

the vectors.

Vector Address

Reset Source

CCR

Mask

Local Enable

$FFFE

Power-On Reset (POR)

None

$FFFE

Low Voltage Reset (LVR)

None

$FFFE

External pin RESET

None

$FFFE

Illegal Address Reset

None

$FFFC

Clock monitor reset

None

OSCE Bit in CPMUOSC register

$FFFA

COP watchdog reset

None

CR[2:0] in CPMUCOP register

Table 1-35. Interrupt Vector Locations (Sheet 1 of 2)

Vector Address

Interrupt Source

CCR

Mask

Local Enable

Wake up

from STOP

Wakeup

from WAIT

Vector base + $F8

Unimplemented instruction trap

None

Vector base+ $F6

SWI

None

Vector base+ $F4

XIRQ

X Bit

None

Yes

Vector base+ $F2

IRQ

I bit

IRQCR (IRQEN)

Yes

Vector base+ $F0

RTI time-out interrupt

I bit

CPMUINT (RTIE)

10.6 Interrupts

Vector base+ $EE

TIM timer channel 0

I bit

TIE (C0I)

Yes

Vector base + $EC

TIM timer channel 1

I bit

TIE (C1I)

Yes

Vector base+ $EA

TIM timer channel 2

I bit

TIE (C2I)

Yes

Vector base+ $E8

TIM timer channel 3

I bit

TIE (C3I)

Yes

Vector base+ $E6

TIM timer channel 4

I bit

TIE (C4I)

Yes

Vector base+ $E4

TIM timer channel 5

I bit

TIE (C5I)

Yes

Vector base + $E2

TIM timer channel 6

I bit

TIE (C6I)

Yes

Vector base+ $E0

TIM timer channel 7

I bit

TIE (C7I)

Yes

Vector base+ $DE

TIM timer overflow

I bit

TSCR2 (TOI)

Yes

Vector base+ $DC

TIM Pulse accumulator A overflow

I bit

PACTL (PAOVI)

Yes

Vector base + $DA

TIM Pulse accumulator input edge

I bit

PACTL (PAI)

Yes

Vector base + $D8

SPI0

I bit

SPI0CR1 (SPIE, SPTIE)

Yes

Vector base+ $D6

SCI0

I bit

SCI0CR2

(TIE, TCIE, RIE, ILIE)

Yes

Vector base + $D4

SCI1

I bit

SCI1CR2

(TIE, TCIE, RIE, ILIE)

Yes