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Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT Hoja De Datos

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TWR-S12GN32-KIT
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Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual,
Rev.1.23
200
Freescale Semiconductor
0x000E–0x001B
Non-PIM
Address Range
R
Non-PIM Address Range
W
0x001C
ECLKCTL
R
NECLK
NCLKX2
DIV16
EDIV4
EDIV3
EDIV2
EDIV1
EDIV0
W
0x001D
Reserved
R
0
0
0
0
0
0
0
0
W
0x001E
IRQCR
R
IRQE
IRQEN
0
0
0
0
0
0
W
0x001F
Reserved
R
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
W
0x0020–0x023F
Non-PIM
Address Range
R
Non-PIM Address Range
W
0x0240
PTT
R
0
0
PTT5
PTT4
PTT3
PTT2
PTT1
PTT0
W
0x0241
PTIT
R
0
0
PTIT5
PTIT4
PTIT3
PTIT2
PTIT1
PTIT0
W
0x0242
DDRT
R
0
0
DDRT5
DDRT4
DDRT3
DDRT2
DDRT1
DDRT0
W
0x0243
Reserved
R
0
0
0
0
0
0
0
0
W
0x0244
PERT
R
0
0
PERT5
PERT4
PERT3
PERT2
PERT1
PERT0
W
0x0245
PPST
R
0
0
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
W
0x0246
Reserved
R
0
0
0
0
0
0
0
0
W
0x0247
Reserved
R
0
0
0
0
0
0
0
0
W
0x0248
PTS
R
PTS7
PTS6
PTS5
PTS4
PTS3
PTS2
PTS1
PTS0
W
Table 2-21. Block Register Map (
G3
) (continued)
Global Address
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
= Unimplemented or Reserved