Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT Hoja De Datos
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TWR-S12GN32-KIT
Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual,
Rev.1.23
206
Freescale Semiconductor
2.4.3.3
Port A Data Direction Register (DDRA)
1
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
Write: Anytime
Table 2-23. PORTB Register Field Descriptions
Field
Description
7-0
PB
Port B general-purpose input/output data—Data Register
The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit
value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read.
The associated pin can be used as general-purpose I/O. In general-purpose output mode the port data register bit
value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read.
Address 0x0002 (
)
Access: User read/write
1
1
Read: Anytime
Write: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
W
Reset
0
0
0
0
0
0
0
0
Address 0x0002 (
,
)
Access: User read only
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-4. Port A Data Direction Register (DDRA)
Table 2-24. DDRA Register Field Descriptions
Field
Description
7-0
DDRA
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
0 Associated pin configured as input