Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT Hoja De Datos
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TWR-S12GN32-KIT
S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
381
10.3.2.7
S12CPMU PLL Control Register (CPMUPLL)
This register controls the PLL functionality.
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
no effect.
NOTE
Write to this register clears the LOCK and UPOSC status bits.
NOTE
Care should be taken to ensure that the bus frequency does not exceed the
specified maximum when frequency modulation is enabled.
specified maximum when frequency modulation is enabled.
0x003A
7
6
5
4
3
2
1
0
R
0
0
FM1
FM0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
Figure 10-10. S12CPMU PLL Control Register (CPMUPLL)
Table 10-7. CPMUPLL Field Descriptions
Field
Description
5, 4
FM1, FM0
PLL Frequency Modulation Enable Bits — FM1 and FM0 enable frequency modulation on the VCOCLK. This
is to reduce noise emission. The modulation frequency is f
is to reduce noise emission. The modulation frequency is f
ref
divided by 16. See
for coding.
Table 10-8. FM Amplitude selection
FM1
FM0
FM Amplitude /
f
VCO
Variation
0
0
FM off
0
1
±1%
1
0
±2%
1
1
±4%