Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT Hoja De Datos
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TWR-S12GN32-KIT
S12 Clock, Reset and Power Management Unit (S12CPMU)
MC9S12G Family Reference Manual,
Rev.1.23
394
Freescale Semiconductor
10.3.2.16 Autonomous Periodical Interrupt Rate High and Low Register
(CPMUAPIRH / CPMUAPIRL)
The CPMUAPIRH and CPMUAPIRL registers allow the configuration of the autonomous periodical
interrupt rate
interrupt rate
.
Read: Anytime
Write: Anytime if APIFE=0. Else writes have no effect.
The period can be calculated as follows depending on logical value of the APICLK bit:
APICLK=0: Period = 2*(APIR[15:0] + 1) * f
ACLK
APICLK=1: Period = 2*(APIR[15:0] + 1) * Bus Clock period
NOTE
For APICLK bit clear the first time-out period of the API will show a latency
time between two to three f
time between two to three f
ACLK
cycles due to synchronous clock gate
release when the API feature gets enabled (APIFE bit set)
.
0x02F4
7
6
5
4
3
2
1
0
R
APIR15
APIR14
APIR13
APIR12
APIR11
APIR10
APIR9
APIR8
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-20. Autonomous Periodical Interrupt Rate High Register (CPMUAPIRH)
0x02F5
7
6
5
4
3
2
1
0
R
APIR7
APIR6
APIR5
APIR4
APIR3
APIR2
APIR1
APIR0
W
Reset
0
0
0
0
0
0
0
0
Figure 10-21. Autonomous Periodical Interrupt Rate Low Register (CPMUAPIRL)
Table 10-19. CPMUAPIRH / CPMUAPIRL Field Descriptions
Field
Description
15-0
APIR[15:0]
Autonomous Periodical Interrupt Rate Bits — These bits define the time-out period of the API. See
for details of the effect of the autonomous periodical interrupt rate bits.