Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT Hoja De Datos

Freescale Semiconductor

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This mode can be entered from default mode PEI by performing the following steps:

1. Make sure the PLL configuration is valid.

2. Enable the external oscillator (OSCE bit)

3. Wait for the oscillator to start-up and the PLL being locked (LOCK = 1) and (UPOSC =1).

4. Clear all flags in the CPMUFLG register to be able to detect any status bit change.

5. Optionally status interrupts can be enabled (CPMUINT register).

6. Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0)

Loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well (UPOSC=0).

The impact of loosing the oscillator status (UPOSC=0) in PBE mode is as follows:

•

PLLSEL is set automatically and the Bus Clock is switched back to the PLLCLK.

•

The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the
PLL locks again.

•

The OSCCLK provided to the MSCAN module is off.

Application software needs to be prepared to deal with the impact of loosing the oscillator status at any
time.

All reset sources are listed in

. Refer to MCU specification for related vector addresses and

priorities.

Upon detection of any reset of

, an internal circuit drives the RESET pin low for 512 PLLCLK

cycles. After 512 PLLCLK cycles the RESET pin is released. The reset generator of the S12CPMU waits
for additional 256 PLLCLK cycles and then samples the RESET pin to determine the originating source.

 shows which vector will be fetched.

Power-On Reset (POR)

None

Low Voltage Reset (LVR)

None

External pin RESET

None

Illegal Address Reset

None

Clock Monitor Reset

OSCE Bit in CPMUOSC register

COP Reset

CR[2:0] in CPMUCOP register