Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT Hoja De Datos
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TWR-S12GN32-KIT
48 KByte Flash Module (S12FTMRG48K1V1)
MC9S12G Family Reference Manual,
Rev.1.23
904
Freescale Semiconductor
All bits in the FRSV3 register read 0 and are not writable.
26.3.2.15 Flash Reserved4 Register (FRSV4)
This Flash register is reserved for factory testing.
All bits in the FRSV4 register read 0 and are not writable.
26.3.2.16 Flash Option Register (FOPT)
The FOPT register is the Flash option register.
All bits in the FOPT register are readable but are not writable.
During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash
configuration field at global address 0x3_FF0E located in P-Flash memory (see
configuration field at global address 0x3_FF0E located in P-Flash memory (see
) as indicated
by reset condition F in
. If a double bit fault is detected while reading the P-Flash phrase
containing the Flash nonvolatile byte during the reset sequence, all bits in the FOPT register will be set.
Offset Module Base + 0x000E
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 26-20. Flash Reserved3 Register (FRSV3)
Offset Module Base + 0x000F
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 26-21. Flash Reserved4 Register (FRSV4)
Offset Module Base + 0x0010
7
6
5
4
3
2
1
0
R
NV[7:0]
W
Reset
F
1
1
Loaded from IFR Flash configuration field, during reset sequence.
F
F
F
F
= Unimplemented or Reserved
Figure 26-22. Flash Option Register (FOPT)