Analog Devices AD9714 Evaluation Board AD9714-DPG2-EBZ AD9714-DPG2-EBZ Hoja De Datos

 

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To use the clock distribution chip provided on the evaluation 
board, access the control settings found on the front panel  
of the SPI front panel shown in Figure 7 and described in 
Section I. This allows the single clock source used to be divided 
down and to feed separate clocks to the data and DAC, which 
helps minimize the number of sources necessary to run the 
evaluation board.   

For testing purposes in this user guide, a clock source of 
250 MHz was used with an f

DAC

 of 125 MHz. In order to 

interleave the data, the data clock ratio needs to be twice the 
frequency of the DAC to allow for proper I and Q lineup.  
To achieve this, the DACCLK divide ratio is set to 2 and the 
DATACLK divide ratio is 1. With these settings, the clock chip 
should work properly and the data clock can be checked by 
probing at S11 SMA with an oscilloscope. For better phase noise 
performance, increase the clock signal source frequency and 
choose higher divide ratios for the data and DAC clocks to 
achieve the desired clock rates. 

When using the internal bias resistors, the R

SET

 resistors must be 

enabled and the on-board jumpers removed from the output 
current jumpers (see Table 3). To enable the resistors through 
the VI, press the buttons labeled IRS_EN and QRS_EN (see 
Section VI) of the VI front panel in Figure 7. The default IRSET 
and QRSET code is set to 0, which corresponds to a 2 mA 
output current for the AD971x.  

When testing the AD911x, change the values for the IRSET  
and QRSET codes to 32, which correspond to a 20 mA output 
current appropriate for this board. Changing this code as 
detailed in the SPI Register section of the data sheet allows the 
user to change the output current being set with these internal 
resistors, much like manually changing the jumpers  
on the board. 

To obtain finer adjustments in the DAC gain than those pro-
vided through the full-scale adjustment resistors, the I and Q 
DAC gain registers can be implemented. The gain adjustment 
must be enabled and set in Figure 7 (see Section VII). In addi-
tion, the common-mode level of the channel output stages  
can be changed in this section by setting the IRCML/QRCML 
controls that alter the value of the on-chip IR

SET

/QR

SET

. The four 

different internal resistor options and the corresponding SPI 
codes, which can be found in the data sheet, are shown in  
Table 8. 

16 kΩ 

000000 (default) 

32 kΩ 

011111 

8 kΩ 

100000 

16 kΩ 

111111 

To completely suppress the LO when using the modulator in the 
signal chain, automatic VIs can be used to sweep the codes for 
all of the range and offset settings of the DAC. Section IX of 
Figure 7 contains all of the controls for the AUX DACs, which 
must be enabled through the SPI before use. The AX1RNG/ 
AX2RNG controls determine the swing voltage of the DAC to 
provide a greater or lesser sweep range. Similarly, the AX1ZE/ 
AX2ZE settings control the maximum voltage (offset) attainable 
in the swing. The code settings (AX1D/AX2D) determine 
where along the swing the DAC is set. Depending on the range 
and offset settings, this determines what the output voltage for 
the AUX DAC will be to calibrate and suppress the LO properly.  

Better resolution for the DAC is attainable by decreasing the 
voltage swing, or range, of the part. The offset determines what 
the maximum voltage of that range will be set to when the DAC 
code is set to maximum (1023). The minimum voltage of that 
range can be determined by taking the corresponding offset 
voltage value and subtracting the range voltage value from it; 
this is the voltage that is output when the DAC code is set to the 
minimum (0). 

If the DAC code vs. LO amplitude values of a sweep for a 
specific range and offset are plotted, there should be a visible 
notch trend. The DAC code at the minimum of the graph shows 
the optimal setting for the DAC to suppress the LO. The output 
voltage for those settings is shown on the VI and is helpful in 
determining if the range and offset settings are optimum for the 
AUX DAC’s maximum resolution at that voltage. If the code 
falls on a voltage that can be achieved using a smaller range, and 
sometimes needing a change in offset to achieve the proper 
range placement, this provides an even better performance and 
further suppression of the LO for performance benefits.  

Sweep one DAC at a time while the other is held constant, 
normally around 0.5 V as a starting value. Once the optimized 
settings are found for the first sweep, hold that AUX DAC at  
the determined settings and repeat the sweep technique for the 
second AUX DAC to find its optimal setting. Sometimes a 
second round of sweeps are necessary to get better LO suppres-
sion once the DACs have been initially optimized and even 
better performance can be attained. 

0 

2.0 V 

0 

1.0 V 

1 

1.5 V 

1 

1.5 V 

2 

1.0 V 

2 

2.0 V 

3 

.5 V 

3 

2.5 V 

  

4 

2.9 

V