Atmel Evaluation Board using the SAM7SE Microcontroller AT91SAM7SE-EK AT91SAM7SE-EK Hoja De Datos

6295A–ATARM–27-Mar-07

The rest of the interrupt handler is straightforward. It simply toggles the state (on or off) of one of
the blinking LED. Refer to 

 for more details on how to control LEDs with

the PIO controller.

The primary goal of the Peripheral Interval Timer (PIT) is to generate periodic interrupts. This is
most often used to provide the base tick of an operating system. The PIT uses MCK divided by
16 as its input clock, as well as a 20-bit counter. Each time the counter reaches a programmable
value, an interrupt is generated, and a second counter increments. The latter makes it possible
to never miss a tick, even when the system is overloaded.

The getting started example uses the PIT to provide a 1 ms time base. Each time the PIT inter-
rupt is triggered, a 32-bit counter is incremented. A Wait function uses this counter to provide a
precise way for an application to suspend itself for a specific amount of time.

Since the PIT is part of the System Controller, it is continuously clocked. As such, there is no
need to enable its peripheral clock in the PMC.

The Mode Register contains the Periodic Interval Value (PIV) which indicates to the PIT when to
reset the internal counter. It must be programmed to the number of ticks generated by MCK/16
in one millisecond:

This is done with the following line of code:

AT91C_BASE_PITC->PITC_PIMR = AT91B_MCK / (16 * 1000) - 1;

Before starting the timer, the interrupt must be configured in the AIC. Please refer to 

 for more information about that step. Once the AIC configuration is done, the

interrupt can be enabled in the PIT Mode Register by setting bit PITIEN; the PIT can also be
started in the same operation by setting bit PITEN.

Acknowledging the interrupt is implicitly done when reading the PIT Value Register. This register
contains two values: the current value of the internal counter (CPIV), and the number of ticks
that have been generated since the last read of PIVR (Periodic Interval Counter, PICNT). A sec-
ond register, the PIT Image Register, contains the same values but does not acknowledge the
pending interrupt.

The interrupt handler for the PIT is thus very simple. First, the PIVR value is read to retrieve
PICNT. A global variable is incremented with the number of ticks read.

Note that it is necessary to check whether there really is a pending interrupt on the PIT; since the
system controller interrupt is shared by several peripheral, any of them can have triggered it.
This is verified by reading the Status Register of the PIT; bit PITS is set when an interrupt is
pending.

Finally, using a 32-bit counter may not be always appropriate, depending on how long the sys-
tem should stay up and on the tick period. In the example, a 1 ms tick overflows the counter after
about 50 days; this may not be enough for a real application. In that case, a larger counter can
be implemented.

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