Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Hoja De Datos
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AT91SAM9M10-G45-EK
20
SAM9M10 [SUMMARY]
6355ES–ATARM–12-Mar-13
summarizes the Slave Memory Mapping for each connected Master, depending on the Remap status (RCBx
bit in Bus Matrix Master Remap Control Register MATRIX_MRCR) and the BMS state at reset.
6.3
Peripheral DMA Controller (PDC)
z
Acting as one AHB Bus Matrix Master
z
Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor.
z
Next Pointer support, prevents strong real-time constraints on buffer management.
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to
High priorities):
High priorities):
Table 6-4.
SAM9M10 Masters to Slaves Access with VDEC_SEL = 1 (default)
Master
0
1
2
3
4 & 5
6
7
8
9
10
11
Slave
ARM
926
Instr.
ARM
926
Data
PDC
USB
HOST
OHCI
DMA
ISI
DMA
LCD
DMA
Ethern
et MAC
USB
Device
HS
USB
Host
EHCI
VDEC
0
Internal SRAM 0
X
X
X
X
X
X
-
X
X
X
-
1
Internal ROM
X
X
X
-
-
-
-
-
X
-
-
UHP OHCI
X
X
-
-
-
-
-
-
-
-
-
UHP EHCI
X
X
-
-
-
-
-
-
-
-
-
LCD User Int.
X
X
-
-
-
-
-
-
-
-
-
UDPHS RAM
X
X
-
-
-
-
-
-
-
-
-
VDEC
X
X
-
-
-
-
-
-
-
-
-
2
DDR Port 0
-
-
-
-
-
-
-
-
-
-
X
3
DDR Port 1
-
-
-
-
-
-
X
-
-
-
-
4
DDR Port 2
X
-
X
X
X
X
-
X
X
X
-
5
DDR Port 3
-
X
X
X
X
X
-
X
X
X
-
6
EBI
X
X
X
X
X
X
X
X
X
X
X
7
Internal Periph.
X
X
X
-
X
-
-
-
-
-
-
Table 6-5.
Internal Memory Mapping
Master
Slave
Base Address
RCBx
= 0
RCBx = 1
BMS = 1
BMS
= 0
0x0000 0000
Internal ROM
EBI NCS0
Internal SRAM
Table 6-6.
Peripheral DMA Controller
Instance name
Channel T/R
DBGU
Transmit
USART3
Transmit
USART2
Transmit
USART1
Transmit
USART0
Transmit
AC97C
Transmit
SPI1
Transmit