Atmel Evaluation Kit AT91SAM9260-EK AT91SAM9260-EK Hoja De Datos

16

SAM9260 [SUMMARY]

6221LS–ATARM–15-Oct-12

z

Boot Mode Select

z

Non-volatile Boot Memory can be internal or external

z

Selection is made by BMS pin sampled at reset

z

Remap Command

z

Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory

z

Allows Handling of Dynamic Exception Vectors 

The Bus Matrix of the SAM9260 manages six Masters, which means that each master can perform an access 
concurrently with others, according the slave it accesses is available.

Each Master has its own decoder that can be defined specifically for each master. In order to simplify the addressing, all 
the masters have the same decodings. 

Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.

All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access 
from the Ethernet MAC to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown “-” in 
the following table. 

Master 0

ARM926

™

 Instruction

Master 1

ARM926 Data

Master 2

PDC

Master 3

USB Host DMA

Master 4

ISI Controller

Master 5

Ethernet MAC

Slave 0

Internal SRAM0 4 KBytes

Slave 1

Internal SRAM1 4 KBytes

Slave 2

Internal ROM

USB Host User Interface

Slave 3

External Bus Interface

Slave 4

Internal Peripherals

Master

0  &  1

2

3

4

5

Slave

ARM926 

Instruction & 

Data

Peripheral 

DMA 

Controller

USB Host 
Controller

ISI 

Controller

Ethernet 

MAC

 0

Internal SRAM

4 KBytes

X

X

X

X

X

 1

Internal SRAM

4 KBytes

X

X

X

X

X