Atmel Evaluation Kit AT91SAM9260-EK AT91SAM9260-EK Hoja De Datos
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AT91SAM9260-EK
26
SAM9260 [SUMMARY]
6221LS–ATARM–15-Oct-12
Figure 9-2. Clock Generator Block Diagram
9.5
Power Management Controller
z
Provides:
z
the Processor Clock PCK
z
the Master Clock MCK, in particular to the Matrix and the memory interfaces
z
the USB Device Clock UDPCK
z
independent peripheral clocks, typically at the frequency of MCK
z
2 programmable clock outputs: PCK0, PCK1
z
Five flexible operating modes:
z
Normal Mode, processor and peripherals running at a programmable frequency
z
Idle Mode, processor stopped waiting for an interrupt
z
Slow Clock Mode, processor and peripherals running at low frequency
z
Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped
waiting for an interrupt
waiting for an interrupt
z
Backup Mode, Main Power Supplies off, VDDBU powered by a battery
On Chip
RC OSC
RC OSC
Power
Management
Controller
XIN
XOUT
PLLRCA
Slow Clock
SLCK
SLCK
Main Clock
MAINCK
MAINCK
PLLA Clock
PLLACK
PLLACK
Control
Status
PLL and
Divider B
Divider B
PLLB Clock
PLLBCK
PLLBCK
XIN32
XOUT32
Slow Clock
Oscillator
Main
Oscillator
PLL and
Divider A
Divider A
Clock Generator
OSC_SEL