Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Hoja De Datos
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AT91SAM9G25-EK
1051
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
46.9.1 UTMI PLL Characteristics
46.10 I/Os
Criteria used to define the maximum frequency of the I/Os:
z
Output duty cycle (40%-60%)
z
Minimum output swing: 100 mV to VDDIO - 100 mV
z
Addition of rising and falling time inferior to 75% of the period
Notes: 1.
3.3V domain: V
VDDIOP
from 3.0V to 3.6V, maximum external capacitor = 40 pF
2.
1.8V domain: V
VDDIOP
from 1.65V to 1.95V, maximum external capacitor = 20 pF
46.11 USB HS Characteristics
46.11.1 Electrical Characteristics
Table 46-17. Phase Lock Loop Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
F
IN
Input Frequency
4
12
32
MHz
F
OUT
Output Frequency
450
480
600
MHz
I
PLL
Current Consumption
active mode
5
8
mA
standby mode
1.5
µA
T
Startup Time
50
µs
Table 46-18. I/O Characteristics
Symbol
Parameter
Conditions
Min
Max
Units
FreqMax
VDDIOP powered Pins frequency
MHz
1.8V domain
MHz
Table 46-19. Electrical Parameters
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
R
PUI
Bus Pull-up Resistor on
Upstream Port (idle bus)
Upstream Port (idle bus)
in LS or FS Mode
1.5
k
Ω
R
PUA
Bus Pull-up Resistor on
Upstream Port (upstream port
receiving)
Upstream Port (upstream port
receiving)
in LS or FS Mode
15
k
Ω
Setting time
T
BIAS
Bias settling time
20
µs
T
OSC
Oscillator settling time
With Crystal 12 MHz
2
ms
T
SETTLING
Settling time
F
IN
= 12 MHz
0.3
0.5
ms