Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Hoja De Datos
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AT91SAM9G25-EK
285
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
25.
Bus Matrix (MATRIX)
25.1
Description
The Bus Matrix implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths
between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix
interconnects up to 16 AHB masters to
between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix
interconnects up to 16 AHB masters to
up to 16 AHB slaves. The normal latency to connect a master to a slave is one
cycle except for the default master of the accessed slave which is connected directly (zero cycle latency).
The Bus Matrix user interface is compliant with ARM Advanced Peripheral Bus and provides a Chip Configuration User
Interface with Registers that allow the Bus Matrix to support application specific features.
Interface with Registers that allow the Bus Matrix to support application specific features.
25.2
Embedded Characteristics
z
12-layer Matrix, handling requests from 11 masters
z
Programmable Arbitration strategy
z
Fixed-priority Arbitration
z
Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master
z
Burst Management
z
Breaking with Slot Cycle Limit Support
z
Undefined Burst Length Support
z
One Address Decoder provided per Master
z
Three different slaves may be assigned to each decoded memory area: one for internal ROM boot, one for
internal flash boot, one after remap
internal flash boot, one after remap
z
Boot Mode Select
z
Non-volatile Boot Memory can be internal ROM or external memory on EBI_NCS0
z
Selection is made by General purpose NVM bit sampled at reset
z
Remap Command
z
Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory (ROM or External Flash)
z
Allows Handling of Dynamic Exception Vectors