Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Hoja De Datos
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AT91SAM9G25-EK
377
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
Figure 29-13.Null Setup and Hold Values of NCS and NWE in Write Cycle
29.9.3.5 Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.
29.9.4 Write Mode
The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal
controls the write operation.
controls the write operation.
29.9.4.1 Write is Controlled by NWE (WRITE_MODE = 1)
shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus during
the pulse and hold steps of the NWE signal. The internal data buffers are switched to output mode after the
NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS.
NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS.
Figure 29-14.WRITE_MODE = 1. The write operation is controlled by NWE
NCS
MCK
NWE,
NWR0, NWR1,
NWR2, NWR3
NWR2, NWR3
D[31:0]
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_PULSE
NCS_WR_PULSE
NWE_CYCLE
A
[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NBS2, NBS3,
A0, A1
MCK
D[31:0]
NCS
A
[25:2]
NBS0, NBS1,
NBS2, NBS3,
A0, A1
NBS2, NBS3,
A0, A1
NWE,
NWR0, NWR1,
NWR2, NWR3
NWR2, NWR3