Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Hoja De Datos

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AT91SAM9G25-EK

454

SAM9G25 [DATASHEET]

11032C–ATARM–25-Jan-13

31.2.1 DMA Controller 0

Two Masters

Embeds 8 channels

64-byte FIFO for channel 0, 16-byte FIFO for Channel 1 to 7

Features:

Linked List support with Status Write Back operation at End of Transfer

Word, HalfWord, Byte transfer support.

Memory to memory transfer

Peripheral to memory

Memory to peripheral

The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the
peripherals below. The hardware interface numbers are provided in

Table 31-1

Table 31-1. DMA Channel Definition

Instance name

T/R

DMA Channel HW

Interface Number

HSMCI0

RX/TX

SPI0

USART0

USART1

TWI0

TWI2

UART0

SSC