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AT91SAM9G25-EK
77
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
13.
Advanced Interrupt Controller (AIC)
13.1
Description
The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller,
providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-time
overhead in handling internal and external interrupts.
providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-time
overhead in handling internal and external interrupts.
The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor.
Inputs of the AIC are either internal peripheral interrupts or external interrupts coming from the product's pins.
Inputs of the AIC are either internal peripheral interrupts or external interrupts coming from the product's pins.
The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus permitting higher priority
interrupts to be serviced even if a lower priority interrupt is being treated.
interrupts to be serviced even if a lower priority interrupt is being treated.
Internal interrupt sources can be programmed to be level sensitive or edge triggered. External interrupt sources can be
programmed to be positive-edge or negative-edge triggered or high-level or low-level sensitive.
programmed to be positive-edge or negative-edge triggered or high-level or low-level sensitive.
The fast forcing feature redirects any internal or external interrupt source to provide a fast interrupt rather than a normal
interrupt.
interrupt.
13.2
Embedded Characteristics
z
Controls the Interrupt Lines (nIRQ and nFIQ) of an ARM
®
Processor
z
Thirty-two Individually Maskable and Vectored Interrupt Sources
z
Source 0 is Reserved for the Fast Interrupt Input (FIQ)
z
Source 1 is Reserved for System Peripherals
z
Source 2 to Source 31 Control up to Thirty Embedded Peripheral Interrupts or External Interrupts
z
Programmable Edge-triggered or Level-sensitive Internal Sources
z
Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive External Sources
z
8-level Priority Controller
z
Drives the Normal Interrupt of the Processor
z
Handles Priority of the Interrupt Sources 1 to 31
z
Higher Priority Interrupts Can Be Served During Service of Lower Priority Interrupt
z
Vectoring
z
Optimizes Interrupt Service Routine Branch and Execution
z
One 32-bit Vector Register per Interrupt Source
z
Interrupt Vector Register Reads the Corresponding Current Interrupt Vector
z
Protect Mode
z
Easy Debugging by Preventing Automatic Operations when Protect Models Are Enabled
z
Fast Forcing
z
Permits Redirecting any Normal Interrupt Source to the Fast Interrupt of the Processor
z
General Interrupt Mask
z
Provides Processor Synchronization on Events Without Triggering an Interrupt
z
Write Protected Registers