Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Hoja De Datos
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AT91SAM9G25-EK
871
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
The flag can be read on the COMPE bit of the Interrupt Status Register (ADC_ISR) and can trigger an interrupt.
The High Threshold and the Low Threshold can be read/write in the Comparison Window Register (ADC_CWR).
If the comparison window is to be used with LOWRES bit in ADC_MR set to 1, the thresholds do not need to be adjusted
as adjustment will be done internally. Whether or not the LOWRES bit is set, thresholds must always be configured in
consideration of the maximum ADC resolution.
as adjustment will be done internally. Whether or not the LOWRES bit is set, thresholds must always be configured in
consideration of the maximum ADC resolution.
40.6.8 ADC Timings
Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register,
ADC_MR.
ADC_MR.
A minimal Tracking Time is necessary for the ADC to guarantee the best converted final value between two channel
selections. This time has to be programmed through the TRACKTIM bit field in the Mode Register, ADC_MR.
selections. This time has to be programmed through the TRACKTIM bit field in the Mode Register, ADC_MR.
Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into consideration to
program a precise value in the TRACKTIM field. See the product ADC Characteristics section.
program a precise value in the TRACKTIM field. See the product ADC Characteristics section.
40.6.9 Buffer Structure
The DMA read channel is triggered each time a new data is stored in ADC_LCDR register. The same structure of data is
repeatedly stored in ADC_LCDR register each time a trigger event occurs. Depending on user mode of operation
(ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2) the structure differs. Each data transferred to DMA buffer, carried
on a half-word (16-bit), consists of last converted data right aligned and when TAG is set in ADC_EMR register, the 4
most significant bits are carrying the channel number thus allowing an easier post-processing in the DMA buffer or better
checking the DMA buffer integrity.
repeatedly stored in ADC_LCDR register each time a trigger event occurs. Depending on user mode of operation
(ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2) the structure differs. Each data transferred to DMA buffer, carried
on a half-word (16-bit), consists of last converted data right aligned and when TAG is set in ADC_EMR register, the 4
most significant bits are carrying the channel number thus allowing an easier post-processing in the DMA buffer or better
checking the DMA buffer integrity.
40.6.10 Write Protected Registers
To prevent any single software error that may corrupt ADC behavior, certain address spaces can be write-protected by
setting the WPEN bit in the
setting the WPEN bit in the
(ADC_WPMR).
If a write access to the protected registers is detected, then the WPVS flag in the ADC Write Protect Status Register
(ADC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
(ADC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset by reading the ADC Write Protect Status Register (ADC_WPSR).
The protected registers are:
z
z
z
z
z
z
z
z