Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Hoja De Datos
Los códigos de productos
AT91SAM9G25-EK
932
SAM9G25 [DATASHEET]
11032C–ATARM–25-Jan-13
43.9.2 SSC Clock Mode Register
Name:
SSC_CMR
Address:
0xF0010004
Access:
Read-write
This register can only be written if the WPEN bit is cleared in
.
• DIV: Clock Divider
0 = The Clock Divider is not active.
Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2.
The minimum bit rate is MCK/2 x 4095 = MCK/8190.
The minimum bit rate is MCK/2 x 4095 = MCK/8190.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
DIV
7
6
5
4
3
2
1
0
DIV