Atmel SAM4S Xplained Pro Starter and Evaluation Kit ATSAM4S-XPRO ATSAM4S-XPRO Hoja De Datos
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ATSAM4S-XPRO
SAM4S Series [DATASHEET]
Atmel-11100G-ATARM-SAM4S-Datasheet_27-May-14
566
The glitch filters are controlled by the Input Filter Enable register (PIO_IFER), the Input Filter Disable register
(PIO_IFDR) and the Input Filter Status register (PIO_IFSR). Writing PIO_IFER and PIO_IFDR respectively sets
and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines.
When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the
When the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the
peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch and
debouncing filters require that the PIO Controller clock is enabled.
Figure 31-5.
Input Glitch Filter Timing
Figure 31-6.
Input Debouncing Filter Timing
31.5.10 Input Edge/Level Interrupt
The PIO Controller can be programmed to generate an interrupt when it detects an edge or a level on an I/O line.
The Input Edge/Level interrupt is controlled by writing the Interrupt Enable register (PIO_IER) and the Interrupt
Disable register (PIO_IDR), which enable and disable the input change interrupt respectively by setting and
clearing the corresponding bit in the Interrupt Mask register (PIO_IMR). As input change detection is possible only
by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The
Input Change interrupt is available regardless of the configuration of the I/O line, i.e. configured as an input only,
controlled by the PIO Controller or assigned to a peripheral function.
By default, the interrupt can be generated at any time an edge is detected on the input.
Some additional interrupt modes can be enabled/disabled by writing in the Additional Interrupt Modes Enable
By default, the interrupt can be generated at any time an edge is detected on the input.
Some additional interrupt modes can be enabled/disabled by writing in the Additional Interrupt Modes Enable
register (PIO_AIMER) and Additional Interrupt Modes Disable register (PIO_AIMDR). The current state of this
selection can be read through the Additional Interrupt Modes Mask register (PIO_AIMMR).
MCK
Pin Level
PIO_PDSR
if PIO_IFSR = 0
PIO_PDSR
if PIO_IFSR = 1
1 cycle
1 cycle
1 cycle
up to 1.5 cycles
2 cycles
up to 2.5 cycles
up to 2 cycles
1 cycle
1 cycle
PIO_IFCSR = 0
Divided Slow Clock
Pin Level
PIO_PDSR
if PIO_IFSR = 0
PIO_PDSR
if PIO_IFSR = 1
1 cycle Tdiv_slclk
up to 1.5 cycles Tdiv_slclk
1 cycle Tdiv_slclk
up to 2 cycles Tmck
up to 2 cycles Tmck
up to 2 cycles Tmck
up to 2 cycles Tmck
up to 1.5 cycles Tdiv_slclk
PIO_IFCSR = 1