Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Hoja De Datos
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The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current
Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address
values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed.
Register r15 is used as a program counter (PC), whereas the Current Program Status Register (CPSR) contains
condition code flags and the current mode bits.
Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address
values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed.
Register r15 is used as a program counter (PC), whereas the Current Program Status Register (CPSR) contains
condition code flags and the current mode bits.
In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers (r8 to r14 in FIQ mode or
r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq,
r14_und are similarly used to hold the values (return address for each mode) of r15 (PC) when interrupts and exceptions
arise, or when BL or BLX instructions are executed within interrupt or exception routines. There is another register called
Saved Program Status Register (SPSR) that becomes available in privileged modes instead of CPSR. This register
contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the
current (privileged) mode.
r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq,
r14_und are similarly used to hold the values (return address for each mode) of r15 (PC) when interrupts and exceptions
arise, or when BL or BLX instructions are executed within interrupt or exception routines. There is another register called
Saved Program Status Register (SPSR) that becomes available in privileged modes instead of CPSR. This register
contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the
current (privileged) mode.
In all modes and due to a software agreement, register r13 is used as stack pointer.
The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS) which
defines:
defines:
constraints on the use of registers
stack conventions
argument passing and result return
For more details, refer to ARM Software Development Kit.
The Thumb state register set is a subset of the ARM state set. The programmer has direct access to:
Eight general-purpose registers r0-r7
Stack pointer, SP
Link register, LR (ARM r14)
PC
CPSR
There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S
Technical Reference Manual, revision r1p2 page 2-12).
Technical Reference Manual, revision r1p2 page 2-12).
9.4.7.1 Status Registers
The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers:
hold information about the most recently performed ALU operation
control the enabling and disabling of interrupts
set the processor operation mode
Figure 9-2. Status Register Format
N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags
N Z C V Q
J
I
F T
Mode
Reserved
Mode bits
Thumb state bit
FIQ disable
IRQ disable
Jazelle state bit
Reserved
Sticky Overflow
Overflow
Carry/Borrow/Extend
Zero
Negative/Less than
Sticky Overflow
Overflow
Carry/Borrow/Extend
Zero
Negative/Less than
31 30 29 28 27
24
7 6 5
0