Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Hoja De Datos
Los códigos de productos
AT91SAM9N12-EK
432
SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
PASR/DS/TCR bits are updated before entry into self-refresh mode if DDRSDRC does not share an external bus with
another controller or during a refresh command, and a pending read or write access, if DDRSDRC does share an
external bus with another controller. This type of update is a function of the UPD_MR bit (see
another controller or during a refresh command, and a pending read or write access, if DDRSDRC does share an
external bus with another controller. This type of update is a function of the UPD_MR bit (see
).
The low-power SDR-SDRAM must remain in self-refresh mode for a minimum period of TRAS periods and may remain in
self-refresh mode for an indefinite period. (See
self-refresh mode for an indefinite period. (See
The low-power DDR1-SDRAM must remain in self-refresh mode for a minimum of TRFC periods and may remain in self-
refresh mode for an indefinite period.
refresh mode for an indefinite period.
The DDR2-SDRAM must remain in self-refresh mode for a minimum of TCKE periods and may remain in self-refresh
mode for an indefinite period.
mode for an indefinite period.
Figure 31-17. Self-refresh Mode Entry, Timeout = 0
Figure 31-18. Self-refresh Mode Entry, Timeout = 1 or 2
NOP READ
BST
NOP
PRCHG
NOP
ARFSH
NOP
0
Trp
Enter Self refresh
Mode
Mode
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
DQS[0:1]
Da
Db
D[15:0]
3
DM[1:0]
NOP READ
BST
NOP
0
Da
Db
64 or 128
wait states
wait states
3
PRCHG
NOP
ARFSH NOP
Trp
Enter Self refresh
Mode
Mode
SDCLK
A[12:0]
COMMAND
CKE
BA[1:0]
DQS[1:0]
D[15:0]
DM[1:0]