Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Hoja De Datos

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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

The ARM9EJ-S EmbeddedICE-RT

™

 is supported via the ICE/JTAG port. It is connected to a host computer via an ICE

interface. Debug support is implemented using an ARM9EJ-S core embedded within the ARM926EJ-S. The internal
state of the ARM926EJ-S is examined through an ICE/JTAG port which allows instructions to be serially inserted into the
pipeline of the core without using the external data bus. Therefore, when in debug state, a store-multiple (STM) can be
inserted into the instruction pipeline. This exports the contents of the ARM9EJ-S registers. This data can be serially
shifted out without affecting the rest of the system.

There are two scan chains inside the ARM9EJ-S processor which support testing, debugging, and programming of the
EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG port.

EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG
operations. A chip reset must be performed after JTAGSEL is changed.

For further details on the EmbeddedICE-RT, see the ARM document:

ARM9EJ-S Technical Reference Manual (DDI 0222A).

TMS is the Test Mode Select input which controls the transitions of the test interface state machine.

TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction
Register, or other data registers).

TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment
controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates
them to the next chip in the serial test circuit.

NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM cores and used to reset
the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a Power On Reset output. It is asserted on power on. If
necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods.

TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test and not
by the tested device. It can be pulsed at any frequency. Note the maximum JTAG clock rate on ARM926EJ-S cores is
1/6th the clock of the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an ARM9E running from the 32.768
kHz slow clock.

RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock handling by emulators.
From some ICE Interface probes, this return signal can be used to synchronize the TCK clock and take not care about
the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE
Mode and not in boundary scan mode.

The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes
and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the
association with two peripheral data controller channels permits packet handling of these tasks with processor time
reduced to a minimum.

The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and
that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system
through the ICE interface.

A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal
configuration.

For further details on the Debug Unit, see the Debug Unit section.