Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Hoja De Datos

384

SAM9X25 [DATASHEET]

11054E–ATARM–10-Mar-2014

The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or 
peripheral devices. It has 6 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to interface 
with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and peripheral 
interfacing. Read and write signal waveforms are fully parametrizable. 

The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an 
automatic slow clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate specific 
waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access for page size up 
to 32 bytes.

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6

 Chip Selects Available

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64-Mbyte Address Space per Chip Select

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8-, 16- or 32-bit Data Bus

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Word, Halfword, Byte Transfers

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Byte Write or Byte Select Lines

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Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select

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Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select

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Programmable Data Float Time per Chip Select

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Compliant with LCD Module

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External Wait Request

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Automatic Switch to Slow Clock Mode 

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Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes