Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Hoja De Datos
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AT91SAM9M10-G45-EK
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SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
1.
Round-Robin Arbitration (default)
2.
Fixed Priority Arbitration
The resulting algorithm may be complemented by selecting a default master configuration for each slave.
When a re-arbitration must be done, specific conditions apply. See
19.5.1
Arbitration Scheduling
Each arbiter has the ability to arbitrate between two or more different master requests. In order to avoid burst
breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during
the following cycles:
breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during
the following cycles:
1.
Idle Cycles: When a slave is not connected to any master or is connected to a master which is not cur-
rently accessing it.
rently accessing it.
2.
Single Cycles: When a slave is currently doing a single access.
3.
End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst,
predicted end of burst matches the size of the transfer but is managed differently for undefined length
burst. See
predicted end of burst matches the size of the transfer but is managed differently for undefined length
burst. See
4.
Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master
access is too long and must be broken. See
access is too long and must be broken. See
19.5.1.1
Undefined Length Burst Arbitration
In order to optimize AHB burst lengths and arbitration, it may be interesting to set a maximum for undefined length
bursts (INCR). The Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer. A
predicted end of burst is used as a defined length burst transfer and can be selected from among the following
Undefined Length Burst Type (ULBT) possibilities:
bursts (INCR). The Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer. A
predicted end of burst is used as a defined length burst transfer and can be selected from among the following
Undefined Length Burst Type (ULBT) possibilities:
1.
Unlimited: No predicted end of burst is generated and therefore INCR burst transfer will not be broken by
this way, but will be able to complete unless broken at the Slot Cycle Limit. This is normally the default and
should be let as is in order to be able to allow full 1 Kilobyte AHB intra-boundary 256-beat word bursts per-
formed by some ATMEL AHB masters.
this way, but will be able to complete unless broken at the Slot Cycle Limit. This is normally the default and
should be let as is in order to be able to allow full 1 Kilobyte AHB intra-boundary 256-beat word bursts per-
formed by some ATMEL AHB masters.
2.
1-beat bursts: Predicted end of burst is generated at each single transfer inside the INCR transfer.
3.
4-beat bursts: Predicted end of burst is generated at the end of each 4-beat boundary inside INCR
transfer.
transfer.
4.
8-beat bursts: Predicted end of burst is generated at the end of each 8-beat boundary inside INCR
transfer.
transfer.
5.
16-beat bursts: Predicted end of burst is generated at the end of each 16-beat boundary inside INCR
transfer.
transfer.
6.
32-beat bursts: Predicted end of burst is generated at the end of each 32-beat boundary inside INCR
transfer.
transfer.
7.
64-beat bursts: Predicted end of burst is generated at the end of each 64-beat boundary inside INCR
transfer.
transfer.
8.
128-beat bursts: Predicted end of burst is generated at the end of each 128-beat boundary inside INCR
transfer.
transfer.
Use of undefined length 16-beat bursts or less is discouraged since this generally decreases significantly overall
bus bandwidth due to arbitration and slave latencies at each first access of a burst.
bus bandwidth due to arbitration and slave latencies at each first access of a burst.
If the master does not permanently and continuously request the same slave or has an intrinsically limited average
throughput, the ULBT should be let at its default unlimited value, knowing that the AHB specification natively limits
all word bursts to 256 beats and double-word bursts to 128 beats because of its 1 Kilobyte address boundaries.
throughput, the ULBT should be let at its default unlimited value, knowing that the AHB specification natively limits
all word bursts to 256 beats and double-word bursts to 128 beats because of its 1 Kilobyte address boundaries.
Unless duly needed the ULBT should be let to its default 0 value for power saving.