Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Hoja De Datos

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The following configuration has to be performed:

• Assign EBI_CS1 to the DDR2 controller by setting the bit EBI_CS1A in the EBI Chip

Select Register located in 

the bus matrix memory space.

• Initialize the DDR2 Controller depending on the LP-DDR device and system bus frequency.

The LP-DDR initialization sequence is described in the section “Low-power DDR1-SDRAM Initialization” in
“DDR/SDR SDRAM Controller (DDRSDRC)”.