Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Hoja De Datos

 323

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The Clock Generator User Interface is embedded within the Power Management Controller Interface and is
described in 

The Clock Generator is made up of:

• One Low Power 32768 Hz Slow Clock Oscillator with bypass mode

• One Low-Power RC oscillator

• One 12 MHz Main Oscillator, which can be bypassed

• One 400 to 800 MHz programmable PLLA, capable to provide the clock MCK to the processor and to the 

peripherals. This PLL has an input divider to offer a wider range of output frequencies from the 12 MHz input, 
the only limitation being the lowest input frequency shall be higher or equal to 2 MHz.

The USB Device and Host HS Clocks are provided by a the dedicated UTMI PLL (UPLL) embedded in the UTMI
macro.

Clock Generator Block Diagram

Power 

Management 

Controller

XIN

XOUT

Main Clock
MAINCK

Control

Status

PLLA and 

Divider

PLLA Clock
PLLACK

12M Main 

Oscillator

UPLL

On Chip 
RC OSC

Slow Clock 
SLCK

XIN32

XOUT32

Slow Clock

Oscillator

Clock Generator

RCEN

UPLLCK

OSCSEL

OSC32EN
OSC32BYP