Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Hoja De Datos

 334

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its
last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the
system.

The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the
Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source
number assigned to the peripheral.

The PMC controls 2 signals to be output on external pins PCKx. Each signal can be independently programmed
via the PMC_PCKx registers.

PCKx can be independently selected between the Slow clock, the Master Clock, the PLLACK/PLLADIV2, the UTMI
PLL output and the main clock by writing the CSS and CSSMCK fields in PMC_PCKx. Each output signal can also
be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx. 

Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and
PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of
PMC_SCSR (System Clock Status Register).

Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been
programmed in the Programmable Clock registers.

As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly
recommended to disable the Programmable Clock before any configuration change and to re-enable it after the
change is actually performed. 

1.

Enabling the 12MHz Main Oscillator:

The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In some cases it may
be advantageous to define a start-up time. This can be achieved by writing a value in the OSCOUNT field in
the CKGR_MOR register.

Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR register
to be set. This can be done either by polling the status register or by waiting the interrupt line to be raised if the
associated interrupt to MOSCS has been enabled in the PMC_IER register.

2.

Setting PLLA and divider:

All parameters needed to configure PLLA and the divider are located in the CKGR_PLLAR register.

The DIVA field is used to control divider itself. A value between 0 and 255 can be programmed. Divider output
is divider input divided by DIVA parameter. By default DIVA parameter is set to 0 which means that divider is
turned off.

The OUTA field is used to select the PLLA output frequency range.

The MULA field is the PLLA multiplier factor. This parameter can be programmed between 0 and 254. If MULA
is set to 0, PLLA will be turned off, otherwise the PLLA output frequency is PLLA input frequency multiplied by
(MULA + 1).

The PLLACOUNT field specifies the number of slow clock cycles before LOCKA bit is set in the PMC_SR reg-
ister after CKGR_PLLAR register has been written.

Once the PMC_PLLAR register has been written, the user must wait for the LOCKA bit to be set in the
PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be