Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Hoja De Datos

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with
external devices in Master or Slave Mode. It also enables communication between processors if an external pro-
cessor is connected to the system.

The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a
data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as
“slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple
Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are
always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may
drive its output to write data back to the master at any given time.

A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master gen-
erates a separate slave select signal for each slave (NPCS).

The SPI system consists of two data lines and two control lines:

• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of 

the slave(s). 

• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. 

There may be no more than one slave transmitting data during any particular transfer. 

• Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master 

may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. 

• Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.

• Supports communication with serial external devices

– Four chip selects with external decoder support allow communication with up to 15 peripherals

– Serial memories, such as DataFlash and 3-wire EEPROMs

– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors

– External co-processors

• Master or slave serial peripheral bus interface

– 8- to 16-bit programmable data length per chip select

– Programmable phase and polarity per chip select

– Programmable transfer delays between consecutive transfers and between clock and data per chip 

select

– Programmable delay between consecutive transfers

– Selectable mode fault detection

• Very fast transfers supported

– Transfers with baud rates up to MCK

– The chip select line may be left active to speed up transfers on the same device